1. Field of the Invention
The present invention relates to a pipeline A/D converter circuit in which a low bit sub-A/D converter and sub-D/A converter comprise one block and a plurality of such blocks are cascaded, and to a structure of a resistance ladder network used in the circuit.
2. Description of the Related Art
Conventionally, there has been reported a structure of a pipeline A/D converter circuit in which a low bit sub-A/D converter and sub-D/A converter comprise one block and a plurality of such blocks are cascaded. For example, a document 1: Lewis, S. H., and Gray, P. R., xe2x80x9cA pipelined 5-Msample/s 9-bit Analog-to-Digital Converter,xe2x80x9d Proceedings of IEEE International Symposium on Circuits and Systems, pp.954-961, 1987 discloses a pipeline A/D converter circuit.
FIG. 8 shows an example of a circuit structure of a conventional pipeline A/D converter circuit. FIG. 9 shows an example of a structure of a sub-A/D converter used in each block. Further, FIG. 10 shows an example of a conventional structure of a resistance ladder for producing a reference voltage of a corresponding to the respective comparators, and then, inputs its output to an encoder 24. The output of the encoder 24 is outputted from sub-A/D converter circuit output terminals 37 and 38 through latches 25 and 26.
This output is inputted to a sub-D/A converter circuit 5 of FIG. 8, and is converted into an analog voltage equivalent to 2-bit digital data, and then, the voltage is subtracted from the output signal of the sample-and-hold circuit 39 in an adding circuit 11. The output of the adding circuit 11 is amplified twice by an amplifying circuit 8, and is inputted to the second stage sub-A/D converter circuit 2 and a second stage MDAC 15 from an MDAC output terminal 18. A signal waveform vout1 at the MDAC output terminal 18 is shown in FIG. 11B.
The signal input to the second stage sub-A/D converter circuit 2 and the second stage MDAC 15 from the MDAC output terminal 18 is processed in the same procedure as the first stage, and is input to the third stage sub-A/D converter circuit and a third stage MDAC 16. A signal waveform vout2 at an MDAC output terminal 19 is shown in FIG. 11C. An interval between V1 and V2 or between V2 and V3 is halved since the gain of the amplifying circuit 8 of the former stage MDAC 14 is twice. Here, attention should be paid to the fact that a changing point of a saw tooth wave of the waveform vout1 shown in FIG. 11B is just coincident with a changing point of a saw tooth wave of the waveform vout2 shown in FIG. 11C.
The signal input to the third stage sub-A/D converter circuit 3 and the third stage MDAC 16 from the MDAC output terminal 19 is processed in the same procedure as the first stage and is input to the fourth stage sub-A/D converter circuit 4. A signal waveform vout3 at an MDAC output terminal 20 is shown in FIG. 11D. Here, attention should be paid to the fact that the changing point of the saw tooth wave of the waveform vout1 shown in FIG. 11B, the changing point of the saw tooth wave of the waveform vout2 shown in FIG. 11C, and the changing point of the saw tooth wave of the waveform vout3 shown in FIG. 11D are all coincident with each other.
The outputs of the sub-A/D converter circuits 1, 2, 3 and 4 of the respective stages pass through a digital correction circuit 52, and then, are taken out as the output of this A/D converter circuit.
However, in the conventional pipeline A/D converter circuit, since the reference voltages used in the sub-A/D converter circuits of the respective stages are equal to each other, when the output of the first stage sub-A/D converter circuit is changed, the outputs of the sub-A/D converter circuits of all stages are changed all at once. Thus, there has been a disadvantage that as shown in FIGS. 11A to 11D, the MDAC outputs of the respective stages are largely changed all at once, and differential nonlinear (xe2x80x9cDNLxe2x80x9d) errors at the respective stages are added.
Here, a description will be made on why a large DNL error is caused when the MDAC output is largely changed. Conventionally, there is reported an MDAC technique for outputting a voltage obtained by subtracting an analog voltage corresponding to a digital input from an input voltage. For example, a document 2: Ahn, G., Choi, H, Lim, S., Lee, S., and Lee, C., xe2x80x9cA 12-b, 10-MHz, 250-mW CMOS A/D Converter,xe2x80x9d IEEE journal of Solid-State Circuits, pp. 2030-2035, 1996 discloses a circuit example of an MDAC. FIG. 13 shows an example of a circuit structure of a general 2-bit MDAC. The operation of this circuit becomes as follows. The 2-bit MDAC circuit operates at two clock phases land 2. First, at the clock phase 1, an inverting input terminal and an output terminal of an operational amplifier 73 are short-circuited by a switch 74, and a voltage of the inverting input terminal becomes nearly equal to a voltage of a noninverting input terminal, that is, a ground (GND) level (this is generally called imaginary grounding).
Capacitors 70, 71 and 72 are connected between an analog input voltage and the inverting input terminal of the operational amplifier, and the analog input voltage is sampled. Next, at the clock phase 2, the switch between the inverting input terminal and the output terminal of the operational amplifier 73 is switched off. One terminal of the two terminals of the capacitor 72 at the side where it is not connected to the inverting input terminal of the operational amplifier 73 is connected to the output of the operational amplifier 73 by a switch 77. One terminal of the two terminals of the capacitor 70 at the side where it is not connected to the inverting input terminal of the operational amplifier 73 is connected to Vref or GND by a switch 75 controlled by the MSB of a digital input of the MDAC. For example, when the MSB [bit] of the digital input of the MDAC is 1, it is connected to Vref, and when the MSB bit of the digital input of the MDAC is 0, it is connected to GND. One terminal of the two terminals of the capacitor 71 at the side where it is not connected to the inverting input terminal of the operational amplifier is connected to Vref or GND by a switch 76 controlled by the LSB bit of the digital input of the MDAC.
For example, when the LSB of the digital input of the MDAC is 1, it is connected to Vref, and when the LSB of the digital input of the MDAC is 0, it is connected to GND. At this time, the output voltage Vout of the MDAC is obtained by the following expression.
Vout=Vin+2(Vinxe2x88x92b1Vref)+(Vinxe2x88x92b0Vref)
Here, b1 and b0 express the MSB and the LSB of the digital input of the MDAC, respectively. Besides, it is assumed that an open loop gain of the operational amplifier 73 is infinite.
Like this, in the circuit in which the inverting input terminal of the operational amplifier is made imaginary grounding by performing negative feedback, the voltage of the output terminal is obtained with the voltage (imaginary grounding) of the inverting input terminal as the reference. Thus, as the voltage of the inverting input terminal is deviated from the GND level in an example of FIG. 13, an error at the output terminal becomes large. In an actual circuit, an open loop gain of an operational amplifier is a finite value, and a voltage variation corresponding to a value obtained by dividing a voltage of an output terminal by the open loop gain of the operational amplifier is generated at an inverting input terminal. Thus, as the voltage variation of the output terminal of the operational amplifier becomes large, the error at the output terminal becomes large. Especially, it becomes remarkable as the open loop gain of the operational amplifier becomes small.
At the respective stages, when the output of the sub-A/D converter circuit is changed, the output voltage of the MDAC is largely changed. At this time, a DNL error in the MDAC output becomes largest. In the conventional A/D converter circuit constructed as shown in FIG. 8, since the reference voltages used in the sub-A/D converter circuits of the respective stages are equal to each other, when the output of the first stage sub-A/D converter circuit is changed, the outputs of the sub-A/D converter circuits of all stages are changed all at once. Thus, the output voltages of the MDACs are also changed at the same timing.
For example, in FIG. 11B, it is assumed that at the timing (indicated by a dotted line) when the output voltage vout1 is largely changed, a DNL error of 0.8 LSB is generated since the open loop gain of the operational amplifier used for the MDAC is small. As shown in FIG. 11C, the output voltage vout2 is also largely changed at the same timing. If the magnitude of a voltage of an error generated by a large change of the output in the output voltage vout2 is equal to that in the voltage vout1, and further, if the amplification of the amplifying circuit 8 is 2, the DNL error generated in the single second stage MDAC 15 becomes 0.4 LSB of half of the DNL error generated in the single first stage MDAC 14. Thus, the DNL error in the output voltage vout2 becomes 1.2 LSB of the addition of the DNL error of 0.8 LSB generated in the single first stage MDAC 14 and the DNL error of 0.4 LSB generated in the single second stage MDAC 15.
Similarly, if the magnitude of a voltage of an error generated by a large change of the output in the output voltage vout3 is equal to that in the voltage vout1, and the amplification of the amplifying circuit 9 is 2, the DNL error generated in the single third stage MDAC 16 becomes 0.2 LSB of 1/4 of the DNL error generated in the single first stage MDAC 14. Thus, the DNL error in the output voltage vout3 becomes 1.4 LSB of the addition of the DNL error of 0.8 LSB generated in the single first stage MDAC 14, the DNL error of 0.4 LSB generated in the single second stage MDAC 15, and the DNL error of 0.2 LSB generated in the single third stage MDAC 16.
As a result, there has been a problem in that when the first stage sub-A/D converter output is changed, the MDAC outputs of the respective stages are largely changed all at once, and the DNL errors at the respective stages are added.
In order to solve the above problems, according to the present invention, in a resistance ladder circuit used for reference voltages of comparators in a sub-A/D converter, in addition to a main resistor dominating a total resistance value of the resistance ladder, an auxiliary resistor having a resistance value of half or less of that of the main resistor is used, so that an offset is formed in the input and output characteristics of sub-A/D converter circuits, and a discrepancy occurs in the input and output characteristics of a second stage or subsequent stage sub-A/D converter.
In an A/D converter circuit constructed as described above, there is a difference between the timing when the output of the first stage sub-A/D converter circuit is changed and the timing when the output of the sub-A/D converter circuit of the second stage or subsequent stage is changed. Thus, since the difference exists between the timing when the first stage MDAC output is largely changed and the timing when the second stage or subsequent stage MDAC output is largely changed, DNL errors at the respective stages are not added. Thus, since the DNL error in the entire circuit is substantially controlled by the DNL error of the first stage MDAC, the DNL error can be decreased as compared with the prior art.
In the present invention, for the purpose of causing the offset in the input and output characteristics of the first stage sub-A/D converter and the second stage or subsequent stage sub-A/D converter, in the resistance ladder circuit, in addition to the main resistor dominating the total resistance value of the resistor ladder, the auxiliary resistor having the resistance value of half or less of that of the main resistor is used, so that the input and output characteristics of the sub-A/D converter circuits are made to have the offset.
In the sub-A/D converter circuits using the thus constructed resistance ladder, the offset occurs in the input and output characteristics in the first stage sub-A/D converter circuit and the second stage sub-A/D converter, and the timing when the output of the first stage sub-A/D converter circuit is largely changed is shifted from the timing when the output of the second stage or subsequent stage MDAC is largely changed. Thus, the DNL error generated in the single second stage or subsequent stage MDAC is not added to the DNL error generated in the first stage MDAC, and the DNL error can be decreased as compared with the normal pipelined AD converter circuit.